The present invention relates to semiconductor manufacturing technology, and more particularly to a method of forming a FinFET device.
Fin field-effect transistor (FinFET) technology is used in advanced semiconductor devices with technology nodes at or below 22 nm to effectively control the short channel effects that arise as the channel length of the transistor is reduced by scaling.
A conventional fabrication process of a FinFET device typically includes the following steps; first, a buried oxide layer is formed on a silicon substrate to obtain a silicon-on-insulator (SOI) structure, a silicon layer is then formed on the silicon-on-insulator structure. The silicon layer may be monocrystalline silicon or polycrystalline silicon. Next, the silicon layer is patterned and etched to form the fin for the FinFET. Thereafter, a gate electrode is formed on opposite sides of the fin, and a stress layer of silicon germanium is formed on opposite ends of the fin.
The conventional process of fabricating a FinFET structure faces substantial challenges, as the height of the fin is between about 30 nm and about 40 nm at the 22 nm or smaller technology node, the fin width is then only between about 12 nm and about 17 nm corresponding to a certain aspect ratio. Thus, the process of fabricating a fin requires the use of smaller lithographic and etch feature size, leading to a limit of the resolution of lithographic and etch processes, so that the fin may be prone to structural collapse during the patterning of the fin. Furthermore, there may be a substantial fluctuation in the threshold voltage of the fin formed by the conventional process due to deviation in the process control of the line width and edge roughness of the fin.
Therefore, a need exists for a method of fabricating a fin having a uniform shape and size without using the patterning and etch processes.